Semiconductor memories are widely used in electronic systems for storing data. A common type of a semiconductor memory is a dynamic random access memory (DRAM). A DRAM typically includes millions or billions of individual DRAM memory cells, each cell storing one bit of data. A DRAM memory cell typically includes an access field effect transistor (FET) and a storage capacitor. The access FET allows transfer of data charge to and from the storage capacitor during read and write operation. In addition the data charge on the storage capacitor is periodically refreshed via the access FET during a refresh operation.
The semiconductor industry is being driven to decrease a size of memory cells located on a semiconductor memory. The miniaturization is generally needed to accommodate the increasing density of circuits necessary for today's semiconductor memories.
The desire of even higher level of circuit integration has stimulated three-dimensional integration of the memory cells in particular of the storage capacitors. Three-dimensional storage capacitors such as deep trench capacitors or stack capacitors are now extensively used in memory cells to reduce the cell array.
Semiconductor memories exist not only a stand-alone memory cell array but are also embedded in processor chips including support devices. The performance of embedded memory cell array in particular with respect to its signal speed is improved since bandwidth problems are reduced due to the elimination of an interface circuitry and of package leads. In future semiconductor market embedded high-speed memories become even more important. The desire of an increased speed of the memory devices can be notably achieved by shrinking the support devices.
The individual components of both the memory cell array and the support devices are generally realized by means of silicon planar technique. The silicon planar technique comprises a sequence of process steps, each process step acting over the whole area of a semiconductor surface and by means of suitable masking layers leading in a targeted manner to a local alteration of the semiconductor material to form the components.
A process of manufacturing an integrated circuit comprises hundreds of process steps which may be divided into three main sections: a front end of line (FEOL) process, a middle of line process (MOL) and a back end of line process (BEOL). During the FEOL processing the electronic devices of the integrated circuit are formed. In a standard process of manufacturing a DRAM memory the FEOL processing include forming the memory cell array, each memory cell including an access FET and a storage capacitor. Concurrently the logic devices in particular logic transistors of the support region are formed.
In the standard DRAM processing the MOL processing is almost completed with a so-called retention anneal step. Said retention anneal step is performed to remove crystal defects especially in the capacitor regions of the memory cells whereby a retention time of the DRAM cell is set and thus the functionality of the DRAM cell is ensured. Said retention anneal process is usually a furnace anneal process wherein temperature is rammed up to temperatures higher than approximately 800° C.
The circuit wiring is subsequently provided during the BEOL processing which usually starts with the formation of a contact layer (metallization 0) of the integrated circuit.
In a standard DRAM process the MOL processing includes a deposition of a diffusion layer covering both the memory cell array and the support region. On top of the diffusion layers a dielectric layer preferable an BPSG layer is provided which is exposed to a heating step to make it flow so that a densification of the layer takes place. The BPSG layer is subsequently planarised preferable by means of a chemical mechanical polishing process.
In the BEOL processing of the DRAM succeeding the MOL processing contact plugs to contact the access FETs of the memory cells and the logic devices of the support region are formed establishing a first metallization plane (metallization 0). Then further metallization layers are disposed to interconnect memory cells and the logic devices to enable access for reading and writing operations of the memory cells controlled by the logic devices.
In order to form integrated circuits having high speed support devices with a small layout it is necessary to create device junctions having sharp borderlines and a small penetration depth, so-called ultra-shallow junctions. Moreover, logic devices in the support region of DRAM memories having improved electrical characteristics are achieved by employing new materials such as high-k dielectics in the capacitor. However, both ultra-shallow junctions and high-k dielectics usually stands a limited maximum temperature. In the standard process of manufacturing DRAM memories however the final retention anneal is carried out with temperatures of more than 800° C. Such a high maximum temperature damages ultra-shallow junctions causing a dopant diffusion which results in a high junction leakage. Moreover many high-k dielectics lose their improved electrical characteristics when applying a temperature above 800° C.